Machine-Win
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| Parameter | Specification |
|---|---|
| Includes Pattern Generation (Stimulus) | No |
| Maximum memory depth | 128 Mpts |
| Maximum timing speed | 5 GHz Conventional / 12.5 GHz Timing Zoom |
| Number of channels | 34 |
| Protocols | DDR4, DDR3, DDR2, DDR, LPDDR4, LPDDR3, LPDDR2, LPDDR |
| Signal type | Single - ended differential |
| Type | Portable Logic Analyzer |
| Models | 16861A | 16862A | 16863A | 16864A |
|---|---|---|---|---|
| Channels | 34 (32 data and 2 clock) | 68 (64 data and 4 clock) | 102 (96 data and 6 clock) | 136 (128 data and 8 clock) |
| Sampling option: Single clock - Clock (clock is on Pod 1) | 1 | 1 | 1 | 1 |
| Sampling option: Single clock - Clock qualifiers | 1 | 3 | 4 | 4 |
| Sampling option: Single clock - Reset qualifier | 0 | 0 | 0 | 1 |
| Sampling option: Multiple clocks - Clocks or clock qualifiers | 2 | 4 | 4 | 4 |
| Sampling option: Multiple clocks - Reset qualifier | 0 | 0 | 0 | 0 |
